Empowering parallel computing with Field Programmable Gate Arrays

https://parco.org/keynotes.html (large view)

https://parco.org/keynotes.html

(30-09-2019) During the international conference "Parallel Computing" in Prague, 10-13 September 2019, prof. Erik D'Hollander gave a keynote about empowering parallel computing with field programmable gate arrays.

FPGAs complement GPUs to accelerate computations in areas such as irregular parallelism and energy consumption. Standard languages for both accelerators such as OpenCL are on the rise. However, both the fixed and reconfigurable architectures require a different compiler and programming style. In his talk Erik D'Hollander focused on high-level synthesis tools to shorten the development time and to improve the quality of the hardware designs. In particular, he stressed the architectural differences between two popular accelerators, FPGAs and GPUs. These differences require another algorithmic approach, compiler directives, language pragmas and target applications, even when using a common language such as OpenCL for both accelerators. 

Looking at the future he stressed the need for architectural improvements to obtain a tighter integration between flexible reconfigurable FPGAs and fast multi-core processors. This was illustrated by recent results obtained using the Heterogeneous Architecture Research Platform (HARP-2) developed by Intel.