Lieven Eeckhout - DPMP

Onderstaande beschrijving is in het Engels:

Lieven Eeckhout (PhD, 2002) is an Associate Professor at Ghent University, Belgium.

His main research interests include

  • Computer architecture and the hardware/software interface in general
  • Performance modeling and analysis
  • Simulation methodology
  • Workload characterization in particular.

He received two IEEE Micro Top Picks Awards. He also recently wrote a synthesis lecture on "Computer Architecture Performance Evaluation Methods" published by Morgan and Claypool.

He graduated 8 PhD students, and currently supervises 4 postdoctoral researchers and 8 PhD students.

He participates in the ExaScience Lab, part of Intel Labs Europe, focusing on architectural simulation techniques for exascale systems.

He was recently awarded an ERC Starting Independent Researcher Grant


Contact:

Publications: http://lib.ugent.be/bibliografie/801001255603

Website: https://www.elis.ugent.be

Dependable Performance on Many-thread Processors (DPMP)

Contemporary microprocessors seek at improving performance through thread-level parallelism by co-executing multiple threads on a single microprocessor chip.

Projections suggest that future processors will feature multiple tens to hundreds of threads, hence called many-thread processors.

Many-thread processors, however, lead to non-dependable performance: co-executing threads affect each other's performance in unpredictable ways because of resource sharing across threads.

Failure to deliver dependable performance leads to missed deadlines, priority inversion, unbalanced parallel execution, etc. This will severely impact the usage model and the performance growth path for many important future and emerging application domains (e.g., media, medical, datacenter).

DPMP envisions that performance introspection using a cycle accounting architecture that tracks per-thread performance, will be the breakthrough to delivering dependable performance in future many-thread processors.

To this end, DPMP will develop a hardware cycle accounting architecture that estimates single-thread progress during many-thread execution.

The ability to track per-thread progress enables system software to deliver dependable performance by assigning hardware resources to threads depending on their relative progress.

Through this cooperative hardware-software approach, this project addresses a fundamental problem in multi-threaded ad multi/many-core processing.