Lieven Eeckhout (PhD 2002) is a Full Professor at Ghent University, Belgium, where he is currently leading a research group of eight PhD and postdoctoral researchers. His research interests include computer architecture and the hardware/software interface, with a specific emphasis on performance evaluation and modeling, and dynamic processor resource management. He was elevated to IEEE Fellow in 2018, and he received the 2017 ACM SIGARCH Maurice Wilkes Award and the 2017 ACM SIGPLAN OOPSLA Most Influential Paper Award. He is the recipient of a European Research Council (ERC) Starting Grant, Advanced Grant and three Proof-of-Concept Grants.
He served as program chair for several top-tier conferences including ISCA 2020, HPCA 2015, CGO 2013 (co-chair) and ISPASS 2009; he served as general chair for ISPASS 2010; and served as the Chair of TCCA (2017-2018). He served as Editor-in-Chief of IEEE Micro (2015-2018), Associate Editor-in-Chief of IEEE Computer Architecture Letters and IEEE Micro, and Associate Editor of IEEE Transactions on Computers, IEEE Computer Architecture Letters and ACM Transactions on Architecture and Code Optimization. He has served as technical program committee member for 50+ top-tier computer architecture conferences.
Description of the project
There are two major flavours of processor core microarchitectures, namely the in-order core and the out-of-order core. Out-of-order processors deliver high performance while incurring high design complexity, large chip area and high power consumption. In-order processors on the other hand feature low complexity, small chip area and low power consumption, but deliver limited performance. There is a clear need for a novel core microarchitecture that delivers high performance at low hardware complexity, low cost and low power consumption. This is of particular interest for mobile and edge devices (e.g., tablets, smartphones, smartwatches, etc.) where increasingly high performance is needed at low cost and low power consumption. The mobile and edge device market is a huge market which continues to grow. High-performance out-of-order processors are too costly and too power-hungry, while in-order processors deliver insufficient performance for the increasingly high-performance demands of emerging mobile and edge workloads and use cases.
We propose a novel core microarchitecture, called the Forward Slice Core (FSC) microarchitecture, which provides high performance at low cost and low power consumption. FSC achieves a dramatic improvement in efficiency by replacing the expensive and high-complexity out-of-order hardware with much simpler in-order hardware queues into which instructions are intelligently steered for high performance using the notion of a load's forward slice. FSC has the potential to improve performance per Watt per euro by at least an order of magnitude. The overall objective of this PoC project is to build a strong benchmarking and IPR portfolio of the Forward Slice Core microarchitecture. The project will strengthen the evaluation of the FSC proposal through simulation and real-hardware implementation, and develop a strategy for commercialization.
