Lieven Eeckhout - Load Slice Core


Lieven EeckhoutLieven Eeckhout (PhD 2002) is a professor at Ghent University, Belgium, in the Department of Electronics and Information Systems (ELIS), where he is currently leading a research group with a dozen PhD students and postdoctoral researchers. His research interests include computer architecture and the hardware/software interface, with a specific emphasis on performance evaluation and modeling, and dynamic resource management. He is the recipient of the 2017 Maurice Wilkes Award and the 2017 OOPSLA Most Influential Paper Award, and was elevated to IEEE Fellow in 2018. Other awards include two IEEE Micro Top Pick selections (2007 and 2010), the ISPASS 2013 Best Paper Award, and Best Paper Nominations at PACT 2014 and ISPASS 2012 through 2016. He served as the Program Chair for ISPASS 2009, CGO 2013 and HPCA 2015, and General Chair for ISPASS 2010. He is the current Chair of the IEEE Computer Society Technical Committee on Computer Architecture (TCCA). He is the editor-in-chief of IEEE Micro (2015-2018), and associate editor of IEEE Computer Architecture Letters (2013-2015), IEEE Transactions on Computers (2016-present) and ACM Transactions on Architecture and Code Optimization (2010-2017). He is the recipient of a European Research Council (ERC) Starting Grant and Advanced Grant; two of his PhD students recently founded CoScale, a spin-off in data center monitoring.



Load Slice Core: A Power and Cost-Efficient Microarchitecture for the Future

The ideal processor building block is a power and cost-efficient core that maximizes the extraction of memory hierarchy parallelism, a combination that neither traditional in-order nor out-of-order cores provide. We propose the Load Slice Core microarchitecture, a restricted out-of-order engine aimed squarely at extracting memory hierarchy parallelism, which, according to preliminary results, delivers a nearly 8 times higher performance per Watt per euro compared to an out-of-order core. The overarching objective of this project to fully determine the potential of the Load Slice Core as a key building block for a novel multi-core processor architecture needed in light of both current and future challenges in software and hardware, including variable thread-level parallelism, managed language workloads, the importance of sequential performance, and the quest for significantly improved power and cost efficiency. We anticipate significant improvement in multi-core performance within the available power budget and cost by combining chip-level dynamism to cope with variable thread-level parallelism along with the inherent power- and cost-efficient Load Slice Core design.